Lidé na fakultě
Ing. Petr Struhovský, Ph.D.

2012, Radioengineering, 2012 (3), p. 898-903), ISSN 1210-2512

This paper deals with a prospective approach of modeling, design evaluation and error determination applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. Design Evaluation methodology was successfully applied to Nyquist rate cyclic converters in our works [13]. Now, we extend its principles to pipelined architecture. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed on the production line in term of integral and differential nonlinearity. This is backgrounded by the fact that the knowledge of ADC performance contributors provided by the proposed method helps to adjust the values of on-chip converter components so as to equalize (and possibly minimize) the total non-linearity error. In this paper, the design evaluation procedure is demonstrated on a system design example of pipelined A/D converter. Significant simulation results of each stage of the design evaluation process are given, starting from the INL performance extraction proceeded in a powerful Virtual Testing Environment implemented in Maple™ software and finishing by an error source simulation, modeling of pipelined ADC structure and determination of error source contribution, suitable for a generic process flow.

Článek v periodiku excerpovaném SCI Expanded

2008, Measurement Science Review, 8 (4), p. 78-81), ISSN 1335-8871

This paper deals with a new concept of virtual testing engine for analogue-to-digital converters (ADCs). The whole system consists of program procedures to extract the most important ADC errors expressed in terms of integral and differential non-linearity (INL and DNL). The developed testbench is especially suitable for educational purpose because of modular conception of the system. The proposed testing engine is implemented in Maple™, bringing an ideal possibility to make a complex system for the simulations of ADC at the virtual level as well as at the circuit level.

Článek v periodiku excerpovaném SCI Expanded

2008, 16th IMEKO TC4 International Symposium and 14th International Workshop - Proceedings, University of Florence), p. 1103-1108), ISBN 978-88-903149-3-3

This paper deals with a prospective approach of modeling and design evaluation applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed in term of integral and differential nonlinearity.

Stať ve sborníku z mezinár. konf.

2008, Digital Technologies 2008, Žilina, Žilinská universita, Elektrotechnická fakulta), ISBN 978-80-8070-953-2

This paper deals with a prospective approach of modeling and design evaluation applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed in term of integral and differential non-linearity.

Stať ve sborníku z mezinár. konf.

2008, Proc. of 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008 (DDECS'08), Los Alamitos, IEEE Computer Society Press), p. 283-286), ISBN 978-1-4244-2276-0

This paper deals with the implementation issues of building Virtual Testing Environment (VTE) for performance extraction of A/D converters. Here, the term "virtual" implies to the fact that the ADC testing is done yet in the circuit design on a base of an ADC model capable to capture the ADC error sources occurring in the integrated circuit structure. The first part of the contribution concerns significant properties of two proposed VTE algorithm implementations, the first one employing Verilog-A behavioral module and the second which is created in Maple environment with built-in libraries for circuit analysis. The performance of both VTE implementations is evaluated at system-level and by simulation of residual non-linearity with an ideal ADC model.

Stať ve sborníku z mezinár. konf.

2007, Electronic Devices and Systems - IMAPS CS International Conference 2007, Brno, Vysoké učení technické v Brně), p. 77-82), ISBN 978-80-214-3470-7

Our work proposes a prospective approach for non-linearity extraction of analog-to-digital converters (ADCs) based on the simulation of ADCs. The testing engine is implemented in MAPLE and consists of program procedures for extracting ADC errors expressed in term of integral and differential non-linearity (INL and DNL). As the performance extraction algorithms we use the Servo-Loop and Histogram method. In our work, we deal with the Nyquist-rate ADCs, and in particular with converters employing the successive approximation technique. The novelty of our solution is the use of effective search algorithms and improved convergence properties, significantly accelerating the conversion.

Stať ve sborníku z mezinár. konf. cizojazyčně

2007, Measurement 2007 - Proceedings of 6th International Conference on Measurement, Bratislava, Institute of Measurement Science of the SAS), p. 98-101), ISBN 978-80-969672-0-9

This paper deals with a new concept of virtual testing engine for analog-to-digital converters (ADCs). The whole system consists of program procedures to extract the most important ADC errors expressed in term of integral and differential non-linearity (INL and DNL). The developed testbench is especially suitable for education purpose because of modular conception of the system. The testing engine proposed is implemented in MAPLE, bringing an ideal possibility to make a complex system for simulating of ADC on the virtual-level as well as on the circuit-level.

Stať ve sborníku z mezinár. konf.

2007, Proceedings CD-ROM of Digital Technologies 2007, Žilina, Slovenská elektrotechnická společnost), ISBN 978-80-8070-786-6

This paper deals with the performance aspects of Virtual Testing Environment (VTE) built for A/D converter performance extraction. Here, the term "virtual" implies the fact that the ADC testing is done yet in the circuit design to identify and possibly optimize the major error sources at transistor-level.

Stať ve sborníku z mezinár. konf.

2007, Design and Diagnostics of Electronic Circuits and Systems, Los Alamitos, IEEE Computer Society), p. 417-421), ISBN 1-4244-1161-0

This paper proposes an innovative concept of a virtual testing environment for analog-to-digital converters (ADCs) applying a suitable conjunction of two performance extraction algorithms - the Servo-Loop and Histogram method. The testing engine proposed is implemented in MAPLE and consists of program procedures to extract ADC errors expressed in term of integral and differential non-linearity (INL and DNL). The novelty of our solution is the use of effective search algorithm and improved convergence properties resulting in a significant reduction of the simulation time.

Stať ve sborníku z mezinár. konf.

2007, Proceedings CD-ROM of Digital Technologies 2007, Žilina, Slovenská elektrotechnická společnost), ISBN 978-80-8070-786-6

Our work deals with macromodels of operational amplifiers (OpAmp) for computer simulations. The reason of usage a macromodel for simulation is the time and cost saving. The greatest advantage of a macromodel is the fact that it allows to analyze the behavior of a specific circuit part without necessity to build the whole system. This is an effective approach for evaluation and acceleration of electronic system design.

Stať ve sborníku z mezinár. konf.

2006, Digital Technologies 2006 - 3rd International Workshop, Žilina, Žilinská universita, Elektrotechnická fakulta), ISBN 80-8070-637-9

Stať ve sborníku z mezinár. konf.

2006, Applied Electronics 2006, Plzeň, ZČU Plzeň), p. 59-62), ISBN 978-80-7043-442-0

This article presents new method for exiting string tensometrical sensors for mechanical tense measurement. This method is based on the synchronized discrete exciting of the string and measuring the string oscillations. The main requirement was self-acting function of the whole system without an external exciting and controlling. The method has been verified on a functional sample.

Stať ve sborníku z mezinár. konf. cizojazyčně

2005, Digital Technologies 2005, Žilina, Slovenská elektrotechnická společnost), p. 80-83), ISBN 80-8070-486-4

Stať ve sborníku z mezinár. konf.